Reconfigurable FFT System on Chip (SOC)

System-on-a-chip (soc) Verification Methods

The advent of system-on-a-chip (SoC) technology is a result of ever increasing transistor density. Unfortunately, this means that verification will pose the greatest problem to design because difficulties in verification scale faster than transistor technology. This paper provides evidence of this effect by citing industry trends, as well as discusses the potential pitfalls in SoC verification....

Automatic Layout of Domain Specific Reconfigurable Subsystems for System-on-a-Chip (SOC)

A heterogeneous reconfigurable System-on-Chip: MORPHEUS

The exponential increase of CMOS circuit complexity along the last decades has lead to two growing problems. The increasing Non-recurring Engineering (NRE) costs of ASICs or System-on-Chips are becoming only affordable to the highest volume applications. Additionally the design methodologies have not kept pace with the rising complexity leading to a rising design productivity gap. Research into...

The MorphoSys Dynamically Reconfigurable System-on-Chip

MorphoSys is a system-on-chip which combines a RISC processor with an array of reconfigurable cells. The important features of MorphoSys are coarse-grain granularity, dynamic reconfigurability and considerable depth of programmability. The first implementation of the MorphoSys architecture, the M1 chip, is currently at an advanced stage and it will operate at 100 MHz. Simulation results indicat...

Parametric Dense Stereovision Implementation on a System-on Chip (SoC)

This paper proposes a novel hardware implementation of a dense recovery of stereovision 3D measurements. Traditionally 3D stereo systems have imposed the maximum number of stereo correspondences, introducing a large restriction on artificial vision algorithms. The proposed system-on-chip (SoC) provides great performance and efficiency, with a scalable architecture available for many different s...